As is well known, to increase the capacity for the integration of semiconductor electronic devices, the resolution of their topographic geometries must be improved so as to minimize the size of the individual devices. This can only be achieved if the planarity of the semiconductor surfaces to which the circuit topography is transferred, as by conventional photolithographic and wet or dry etching techniques, can be improved. In particular, for electronic circuits integrated on semiconductors and incorporating non-volatile memories, this requirement must allow for certain specific constraints.
A first constraint is represented, for example, by the ability to provide insulating dielectric layers with enhanced planarity. Dielectric layers serve to isolate a semiconductor substrate region, wherein MOS components have been formed with their polysilicon gate regions, from an overlying metallization plane. The planarity of the insulating dielectric layer does affect the resolution of planar electric connection patterns on the overlying metallization plane.
Another constraint imposed by the memory circuits is the need for low-temperature fabrication processes, because integrated electronic devices which incorporate non-volatile memories have shallow junctions and metal contacts which are sensitive to high temperatures, especially in the gate regions. High temperatures are responsible for the diffusion phenomenon whereby the dopant chemical species are allowed to migrate into the semiconductor and may render the device inoperative. It should be mentioned, moreover, that the dielectric layer isolating the metallization plane from the substrate underneath is bound to contain dopant species of the N type at high concentrations in virtually all cases.
In fact, non-volatile memories require that an N-doped insulating dielectric layer be provided to promote electric charge retention in the gate regions associated with the memory cells by the well-known mechanism of gettering the movable metal ions into a dielectric including the N dopant. A first known approach to meeting this requirement for optimized planarity within the above constraints is shown in FIGS. 1A and 1B, and provides for the deposition of an insulating dielectric layer of the BPSG type between the semiconductor substrate and the overlying metallization plane using a PECVD technique from a gaseous or a solid source. Planarization is then completed by a thermal treatment in an oven at temperatures close to the melting temperature of the deposited dielectric layer.
This prior approach has the serious drawback that there is the need of using dielectrics with high Phosphorous concentrations, but low Boron concentrations which allow obtaining satisfactory planarization levels only by high temperatures thermal treatments, such as, in the range of 750-850.degree. C. Such thermal treatments are not compatible with the memory devices considered herein, since these dielectric films degrade at temperatures above 850.degree. C.
A second prior approach is shown schematically in FIGS. 2A and 2B which provides for the deposition of dielectric layers formed from non-planarized USG, PSG, and BPSG oxides and being of substantial thickness. Planarization is then achieved by a chemiophysical attack known by the acronym CMP (Chemical Mechanical Polishing). While achieving its objective, not even this approach is devoid of shortcomings inherent to the chemiophysical attacks, such as, the difficultly of control and the high sensitivity to the concentrations of dopants in the dielectric layer.
A third approach, resembling the second approach above, is illustrated in FIGS. 3A and 3B and provides for the deposition of a first, non-planarized dielectric layer having a USG, PSG, BPSG type of oxide with substantial thickness, over which a gel is then deposited using a spinning technique, e.g. a SOG (Spin-On-Glass) which has high viscosity and planarizing properties and allows a second dielectric layer to be formed. Alternatively, a resist could be used. This second dielectric layer is solidified during a subsequent step by a densifying and branching operation, loosely referred to as "polymerization" hereinafter with no limitative implications.
Solidification is illustratively effected at a temperature of 400.degree. C. The planarization of the ultimate dielectric layer is achieved by a plasma or an aqueous solution etching process to thoroughly remove the planarizing dielectric layer of the SOG type, or the resist, and, in part, the first dielectric layer as well.
The drawbacks of this third approach originate from the use of techniques of the etch-back type without masking which are difficult to control because of the different values of the etch rates associated with the two dielectric layers deposited.
This degrades the planarity previously provided by the second dielectric layer of the SOG type.
A fourth approach provides, as shown in FIGS. 4A and 4B, for the formation of a multi-layered dielectric structure which fully covers the semiconductor substrate and comprises: a first insulating dielectric layer, e.g. of silicon oxide; a second, intermediate planarizing dielectric layer, e.g. of SOG; and a third, capping and encapsulating dielectric layer, e.g. of PSG or BPSG. The first dielectric layer is undoped and is deposited by CVD techniques to a predetermined thickness, for the sole purpose of isolating the semiconductor substrate from the subsequent deposition of the intermediate dielectric layer.
The second planarizing layer is formed by depositing, from a liquid source, a material of the SOG type containing silicates and no organic radicals. Such silicates may be lightly doped with phosphorus. These materials are evenly spread over the first dielectric layer by a "spinning" technique, and then solidified by thermal treatments which result in the materials polymerizing at low temperatures, barely higher than 400.degree. C. After that, these materials are stabilized by a thermal treatment with temperatures higher than 700.degree. C. To seal this intermediate dielectric layer, as a potential cause for diffusion of impurities into the substrate, a third dielectric layer, typically of silicon oxide, is deposited by chemical vapor deposition techniques (PECVD, APCVD, SACVD, etc.). This third layer must be doped with impurities of either the N or Phosphorous type to meet the requirements for charge retention to the memory cells integrated on the semiconductor substrate (gettering of movable metal impurities).
A detailed description of this deposition method and the formation of this layered dielectric structure is given in an article entitled INTERLEVEL DIELECTRIC PLANARIZATION WITH SPIN-ON GLASS FILMS by Landon B. Vines of Thomson Components-Mostek Corporation and Satish K. Gupta of Allied Signal Corporation. While being advantageous in many ways, this fourth approach also has a serious drawback in that it uses a silicate SOG for the planarizing intermediate dielectric layer. This type of SOG provides low planarity, due to the small thickness that must be maintained for the spinning step. For this reason, a number of spinning operations (i.e. several steps of even distribution of the solution over the surface) must be performed, each interleaved with thermal treatments, to obtain acceptable levels of planarity. This decreases the repeatability and makes the method difficult to control.
Repeated thermal treatments at temperatures higher than 500.degree. C. may result in contaminants being released which will migrate to the substrate. Another disadvantage brought about by the intermediate dielectric layer of the SOG type is the proneness of this material to cracking at its thickest spots. Large thickness dimensions are desirable from the standpoint of planarity, but are more likely to crack.
For a review of further problems tied to intermediate dielectric layers, reference can be had to an article entitled A SCALABLE MULTILEVEL METALLIZATION WITH PILLAR INTERCONNECTIONS AND INTERLEVEL DIELECTRIC PLANARIZATION by Egil D. Castell, Vivek D. Kulkarni, Paul E. Riley of National Semiconductor Corporation which describes, on page 610, a process for forming an intermediate dielectric layer from a liquid source using an LPCVD technique and a resist type of material to planarize the surface of the dielectric grown. In this case, a single dielectric layer is deposited by two successive depositions of silicon oxide using an LPCVD technique, between which a high-temperature thermal treatment and plasma etching using A.sub.r /CF.sub.4 /O.sub.2 are applied.